A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.
| DONE0 | This bit mirrors the DONE status flag from the result register for A/D channel 0. |
| DONE1 | This bit mirrors the DONE status flag from the result register for A/D channel 1. |
| DONE2 | This bit mirrors the DONE status flag from the result register for A/D channel 2. |
| DONE3 | This bit mirrors the DONE status flag from the result register for A/D channel 3. |
| DONE4 | This bit mirrors the DONE status flag from the result register for A/D channel 4. |
| DONE5 | This bit mirrors the DONE status flag from the result register for A/D channel 5. |
| DONE6 | This bit mirrors the DONE status flag from the result register for A/D channel 6. |
| DONE7 | This bit mirrors the DONE status flag from the result register for A/D channel 7. |
| OVERRUN0 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0. |
| OVERRUN1 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1. |
| OVERRUN2 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2. |
| OVERRUN3 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3. |
| OVERRUN4 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4. |
| OVERRUN5 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5. |
| OVERRUN6 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6. |
| OVERRUN7 | This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7. |
| ADINT | This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |